1. Field of the Invention
This invention relates to electronic circuitry and, more particularly, to a deserializer that contains multiple 1-to-2 demultiplexing cells (xe2x80x9cdemultiplexersxe2x80x9d) arranged in stages, wherein each demultiplexer contains fewer circuit elements and consumes less power than a conventional 1-to-2 demultiplexer.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Communication between nodes of a communication system typically involves a serial bitstream. The bitstream can be formatted in numerous ways and is sent across a wire or wireless medium between nodes of the network. Examples of serial bitstream transfer protocols include Ethernet and Synchronous Optical Network (xe2x80x9cSONETxe2x80x9d), as well as numerous others.
An integral part of the serialized communication between nodes is the transceiver associated with each node. A transceiver, having both a receiver and a transmitter, functions not only to recognize the protocols which envelop the packets of serialized data, but also convert the serial bitstream to multiple bitstreams, if necessary. The conversion from a relatively high bit rate serial bitstream to a parallel set of relatively low bit rate parallel bitstreams takes place within a receiver, and is oftentimes referred to as deserialization. Conversely, the conversion from parallel bitstreams to a serial bitstream occurs within a transmitter, and is oftentimes referred to as serialization.
The serializer and deserializer of the transceiver are normally found within the physical media attachment (xe2x80x9cPMAxe2x80x9d) sublayer of the transceiver. The serializer/deserializer is responsible for supporting multiple encoding or protocol schemes and allowing presentation of those encoding schemes to the upper layers of, for example, the Open System Interconnection (xe2x80x9cOSIxe2x80x9d) model. As the bit transfer rate of the serial bitstream increases, power consumption within the serializer/deserializer can also substantially increase. This is due, in part, to the time-division multiplexing and demultiplexing operations that must take place at a rate at or near the bit transfer rate.
At slower bit rates, shift registers can be used. As the serial bitstream is received on the shift registers, a clock signal shifts the serial bits into the registers and outputs the corresponding parallel bitstreams from each stage of the register. A state machine can be used to output the parallel bits into another register at predetermined times. As the bit rate increases, however, clocking the data storage elements of the shift registers at full, or even half rates, can consume substantial amounts of power within the deserializer.
A popular form of deserializer which can operate at slower clock rates is oftentimes referred to as a pipelined deserializer. A pipelined deserializer essentially arranges the demultiplexers into stages. Each stage can be clocked by a successively slower clock rate. This allows for a majority of the demultiplexing cells, especially in the back-end stages, to operate at much slower clock speeds than the speed at which the serial bitstream is transferred.
While a pipelined deserializer has power saving advantages over conventional shift registers and state machines that are clocked at substantially the same rate as the serial bitstream, pipelined deserializers typically use multiple latches within each demultiplexing cell. Regardless of the clock rate, a demultiplexing cell that has excessive data storage elements (or latches) consumes a great deal more power than a cell having fewer latches. However, typical demultiplexers of a pipelined deserializer are generally limited to having a minimum number of latches and, therefore, are constrained to having a minimum power consumption level that can be intolerable in many applications. For example, if a deserializer is called upon to deserialize bitstreams exceeding one or more Gbits/sec., then conventional demultiplexers found within rather large 1-to-n (where n is large) deserializers will consume undesirable amounts of power in, for example, portable applications.
It would be desirable to introduce a demultiplexer cell, or demultiplexer, within a pipelined deserializer that consumes less power than conventional demultiplexers. It would also be desirable to make the overall demultiplexer small so as to reduce the fan out requirements of any clock signal input to each of the components of the demultiplexer. A smaller and less power consumptive demultiplexer can be used in large 1-to-n deserializers, where n might exceed 16, 32, or even 64 parallel bitstreams.
The problems outlined above are in large part solved by introducing an improved deserializer that uses smaller and less power consumptive demultiplexers arranged in stages within a pipelined architecture. Each demultiplexer is the same and uses no more than three latches. It may be desirable, however, in the last stage of the deserializer, that special demultiplexers be used, each of which might preferably have no more than three latches. The early stage or stages of the pipelined architecture, however, use a demultiplexer having no more than three latches.
Placing the three-latch demultiplexers within the early stages of a deserializer addresses the primary culprit of power consumption within the deserializer. Specifically, in a pipelined deserializer, the first stage will be clocked at the maximum clocking frequency of the deserializer. The clocking frequency of the latches within the first stage is preferably one-half frequency of the serial bitstream. The latches within each successive stage will operate at one-half the preceding stage. Thus, by utilizing three-latch demultiplexers within the early stages, the overall power consumption of the deserializer is substantially reduced. The latter stages would operate at clocking frequencies that might be so slow that regardless of the number of latches, the overall power consumption attributable to those stages would be relatively inconsequential.
A latch is herein referred to as a single storage element. Most conventional demultiplexers use a flip-flop instead of a latch. Specifically, conventional demultiplexers utilize two flip-flops coupled in parallel to receive the serial bitstream. Each flip-flop will thereby produce a corresponding odd-bit serial bitstream or even-bit serial bitstream to effectuate a 1-to-2 demultiplexer. Contrary to a latch having a single storage element, a flip-flop generally has two storage elements connected in series. The first storage element is often referred to as the master latch, and the second storage element is often referred to as the slave latch.
The master and slave latches are typically clocked by complementary clock signals. Employing two master-slave flip-flops, each comprising a pair of latches would therefore constitute four latches instead of the three-latch present design. In addition, since there would be a discrepancy in the phase outcome from the pair of flip-flops, an additional latch would be needed at the output of one of the flip flops to increase the conventional demultiplexer size to five latches, rather than the present three latches. Using three latches rather than five latches at the early stages of the pipelined deserializer will significantly increase the overall size of the deserializer, as well as the power consumption and clock fan out of the deserializer.
Broadly speaking, the present invention contemplates a deserializer and a demultiplexer formed as part of a transceiver, for example. The transceiver can be any device which performs a serializer/deserializer function. The contemplated deserializer could, if necessary, simply operate in reverse as a serializer.
According to one embodiment, the demultiplexer includes a first latch, a second latch, and a third latch. The first and second latches are coupled in series, with an input of the first latch adapted to receive a serial bitstream and the output of the second latch adapted to latch a pair of bits within the serial bitstream onto an output of the demultiplexer. The pair of bits are separated in time by an intervening bit which is not placed on the output of the second latch. Instead, the intervening bit is produced from an output of a third latch. The third latch is coupled in parallel to the first and second latches in order to receive the serial bitstream, similar to the first latch receiving the serial bitstream.
The demultiplexer consists of no more than three latches. A pair of bits arising from the second latch consists of two bits within a series of odd bits of the serial bitstream, and the intervening bit from the output of the third latch consists of one bit within a series of even bits. The odd and even bits are interleaved with one another in order to represent each and every bit within the serial bitstream. The second and third latches preferably receive a common clock signal, and the first latch receives an inverse of that common clock signal. In addition to outputting even and odd bits, the output from the demultiplexer preferably consumes almost the entirety of a cycle of the common clock signal, even though the common clock signal preferably transitions at substantially one-half the bit rate of the serial bitstream.
According to yet another embodiment, a deserializer is provided. The deserializer includes a first demultiplexer, a second demultiplexer, and a third demultiplexer. The first demultiplexer can be found within a first stage that feeds into a second stage. The second and third demultiplexers can be found within the second stage, and are connected in parallel to receive respective odd bits and even bits produced from the first demultiplexer. Preferably, the first, second, and third demultiplexers are substantially the same and each comprise no more than three latches.
The first stage having the first demultiplexer is preferably clocked at one-half the bit rate of the serial bitstream. The second stage having the second and third demultiplexers is clocked by a second clock signal that transitions at preferably one-quarter the bit rate of the serial bitstream. In addition to the second clock being at one-half the frequency of the first clock, the second clock signal is delayed relative to the first clock signal. The amount of delay is preferably less than one-half clock cycle of the second clock signal.
According to yet another embodiment, a method is provided. The method involves deserializing a bitstream by generating a pair of interleaving bitstreams from the bitstream using no more than three latches that are clocked by a first clock signal. Thereafter, another pair of interleaving bitstreams are generated from each of the pair of interleaving bitstreams using no more than three latches that are clocked by a second clock signal transitioning at one-half the frequency of the first clock signal and delayed relative to the first clock signal. The amount of delay is preferably chosen so that the second clock signal can have transitions that are aligned with valid bits coming from the upstream or preceding stage or stages. By delaying the second clock signal relative to the first clock signal, invalid data that was sampled in the preceding stage is not-sampled in the successive stage.